There are serious limitations on scale-out architectures for computers and particularly on maintaining coherency.
Computing architectures based, for example, on ARM and RISC instructions don't support scale-out computing architecture that supports coherent and non-coherent traffic.
Due to limitation with DDR based interface bandwidth it is not possible to match the CPU processing capability with memory interface bandwidth and the I/O bandwidth.
As use case continues to change, it is not possible to support the above requirements with a fixed I/O protocol based computing architecture. Although software defined networking supports flexible I/O protocol, this does not address the memory interface, coherency, and non-coherency issues at the same time.
This presents a technical problem for which a technical solution using a technical means is needed.